ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 96

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.10.6
17.10.7
8042B–AVR–06/10
TIMSKn – Timer/Counter n Interrupt Mask Register
TIFRn – Timer/Counter n Interrupt Flag Register
In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Regis-
ter. To ensure that both the high and the low bytes are written simultaneously when the CPU
writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
isters in 16-bit Mode” on page
• Bit 3 – ICIEn: Timer/Counter n Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 2 – OCIEnB: Timer/Counter n Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCFnB bit is set in the Timer/Counter
Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Counter n Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter n Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter n occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Counter n Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-
ter n Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Counter n occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-
ister – TIFRn.
• Bits 3 – ICFn: Timer/Counter n Input Capture Flag
This flag is set when a capture event occurs, according to the setting of ICENn, ICESn and ICSn
bits in the TCCRnA Register.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
Bit
(0x6E)(0x6F)
Read/Write
Initial Value
Bit
0x15 (0x35)
Read/Write
Initial Value
(See Section “12.” on page
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
90.
52.) is executed when the ICFn flag, located in TIFRn, is set.
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
ICIEn
ICFn
ATmega16HVB/32HVB
R/W
R/W
3
0
3
0
OCIEnB
OCFnB
R/W
R/W
2
0
2
0
OCIEnA
OCFnA
R/W
R/W
1
0
1
0
”Accessing Reg-
TOIEn
TOVn
R/W
R
0
0
0
0
TIMSKn
TIFRn
96