ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 89
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.7.1
17.7.2
17.8
8042B–AVR–06/10
Timer/Counter Timing Diagrams
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCRnA/B to be
initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter
clock is enabled.
Since writing TCNTnH/L will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNTnH/L when using the Output Compare Unit, independently of
whether the Timer/Counter is running or not. If the value written to TCNTnH/L equals the
OCRnA/B value, the Compare Match will be missed.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value.
Figure 17-6. Timer/Counter Timing Diagram, no Prescaling
Figure 17-7 on page 89
Figure 17-7. Timer/Counter Timing Diagram, with Prescaler (f
Figure 17-8 on page 90
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
Figure 17-6 on page 89
shows the same timing data, but with the prescaler enabled.
shows the setting of OCFnA and OCFnB in Normal mode.
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation.
MAX
MAX
ATmega16HVB/32HVB
BOTTOM
BOTTOM
clk_I/O
/8)
Tn
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
89
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