ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 183

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.9
8042B–AVR–06/10
Bus Connect/Disconnect for Two-wire Serial Interface
The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura-
tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected.
Figure 27-22
data and clock lines, respectively.
When the TWI bus is connected, both the SDA and the SCL lines will become high simultane-
ously. If the TWBCIP bit is cleared, the interrupt will be executed if enabled. Once the bus is
connected, the TWBCIP bit should be set. This enables detection of when the bus is discon-
nected, and prevents repetitive interrupts every time both the SDA and SCL lines are high (e.g.
bus IDLE state).
When the TWI bus is disconnected, both the SDA and the SCL lines will become low simultane-
ously. If the TWBCIP bit is set, the interrupt will be executed if enabled and if both lines remain
low for a configurable time period. By adding this time constraint, unwanted interrupts caused by
both lines going low during normal bus communication is prevented. Once the bus is discon-
nected, the TWBCIP bit should be cleared. This enables detection of when the bus is connected,
and prevents repetitive interrupts if the SCL and SDA lines remain low.
Figure 27-22. Overview of Bus Connect/Disconnect.
SDA
SCL
illustrates the Bus Connect/Disconnect logic, where SDA and SCL are the TWI
TWBCIP
START
DELAY ELEMENT
8-BIT DATA BUS
ATmega16HVB/32HVB
TWBCSR
DELAY
OUTPUT
SET TWBCIF
IRQ
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