ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 82

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17. Timer/Counter (T/C0,T/C1)
17.1
17.2
17.2.1
8042B–AVR–06/10
Features
Overview
Registers
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•
•
•
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Timer/Counter n is a general purpose 8-/16-bit Timer/Counter module, with two/one Output
Compare units and Input Capture feature.
ATmega16HVB/32HVB has two Timer/Counters, Timer/Counter0 and Timer/Counter1. The
functionality for both Timer/Counters is described below. Timer/Counter0 and Timer/Counter1
have different Timer/Counter registers, as shown in
The Timer/Counter general operation is described in 8-/16-bit mode. A simplified block diagram
of the 8-/16-bit Timer/Counter is shown in
I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are
listed in the
Figure 17-1. 8-/16-bit Timer/Counter Block Diagram
The Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA and
OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in
signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the
figure.
In 16-bit mode the Timer/Counter consists one more 8-bit register, the Timer/Counter High Byte
Register (TCNTnH). Furthermore, there is only one Output Compare Unit in 16-bit mode as the
two Output Compare Registers, OCRnA and OCRnB, are combined to one 16-bit Output Com-
Clear Timer on Compare Match (Auto Reload)
Input Capture unit
Four Independent Interrupt Sources (TOVn, OCFnA, OCFnB, ICFn)
8-bit Mode with Two Independent Output Compare Units
16-bit Mode with One Independent Output Compare Unit
”Register Description” on page
TCCRnA
TCNTnH
OCRnB
=
Timer/Counter
Count
Clear
TCNTnL
TCCRnB
OCRnA
=
Figure
94.
Control Logic
TOP
17-1. CPU accessible I/O Registers, including
Detector
Edge
”Register Summary” on page
clk
ATmega16HVB/32HVB
=
Tn
Canceler
Fixed TOP value
( From Prescaler )
Noise
Clock Select
Detector
Edge
TOVn (Int. Req.)
OCnA (Int. Req.)
OCnB (Int. Req.)
ICFn (Int. Req.)
Figure 17-1 on page
ICPn1
ICPn0
Tn
256.
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