ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 81

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3
16.3.1
16.3.2
8042B–AVR–06/10
Register Description
TCCRnB – Timer/Counter n Control Register B
General Timer/Counter Control Register – GTCCR
• Bits 2, 1, 0 – CSn2, CSn1, CSn0: Clock Select0, Bit 2, 1, and 0
The Clock Select n bits 2, 1, and 0 define the prescaling source of Timer n.
Table 16-1.
If external pin modes are used for the Timer/Counter n, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
When the TSM bit is written to zero the PSRSYNC bit is cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Bit
(0x80)(0x81)
Read/Write
Initial Value
Bit
0x23 (0x43)
Read/Write
Initial Value
CSn2
0
0
0
0
1
1
1
1
CSn1
0
0
1
1
0
0
1
1
Clock Select Bit Description
TSM
R/W
7
0
R
7
–
0
CSn0
R
6
–
0
0
1
0
1
0
1
0
1
R
6
–
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on Tn pin. Clock on falling edge.
External clock source on Tn pin. Clock on rising edge.
R
5
–
0
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
ATmega16HVB/32HVB
CSn2
R/W
2
0
R
2
–
0
CSn1
R/W
R
1
0
1
–
0
PSRSYNC
CSn0
R/W
R/W
0
0
0
0
TCCRnB
GTCCR
81