ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 212

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.6.1
8042B–AVR–06/10
Serial Programming Algorithm
Figure 30-1. Serial Programming and Verify.
Table 30-10. Pin Mapping Serial Programming
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on OSCSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
High: > 2.2 CPU clock cycles for f
When writing serial data to the ATmega16HVB/32HVB, data is clocked on the rising edge of
SCK.
When reading data from the ATmega16HVB/32HVB, data is clocked on the falling edge of SCK.
See
To program and verify the ATmega16HVB/32HVB in the Serial Programming mode, the follow-
ing sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
Make sure the chip is started as explained in
ger Connect” on page 43
programmer can not guarantee that SCK is held low during power-up. In this case,
”Serial Programming Characteristics” on page 239
Symbol
MOSI
MISO
SCK
MOSI
MOSI
MISO
MISO
SCK
SCK
while RESET and SCK are set to “0”. In some systems, the
Pins
PB5
PB6
PB7
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
RESET
GND
GND
I/O
O
I
I
Section 11.2.1 ”Power-on Reset and Char-
ATmega16HVB/32HVB
for timing details.
V
V
FET
FET
+4.0 - 25.0V
+4.0 - 25.0V
Table 30-12 on page
Serial Data out
Serial Data in
Description
Serial Clock
ck
ck
>= 12 MHz
>= 12 MHz
214):
212