ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 63

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2
14.2.1
14.2.2
8042B–AVR–06/10
High Voltage Ports as General Digital I/O
Configuring the Pin
Reading the Pin
The high voltage ports are high voltage tolerant open collector output ports. In addition they can
be used as general digital inputs.
pin, here generically called Pxn.
Figure 14-2. General High Voltage Digital I/O
Notes:
Each port pin consist of two register bits: PORTxn and PINxn. As shown in
tion” on page
the PINx I/O address.
If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,
the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active, even
if no clocks are running.
The port pin can be read through the PINxn Register bit. As shown in
Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metasta-
bility if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay.
1. WRx, RRx and RPx are common to all pins within the same port. clk
2. The High Voltage Digital Input is not present on PC5.
mon to all ports.
Pxn
66, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at
SLEEP:
clkI/O:
HIGH VOLTAGE DIGITAL INPUT
SLEEP CONTROL
I/O CLOCK
Figure 14-2
SLEEP
(2)
shows a functional description of one output port
(1)
SYNCHRONIZER
RRx:
WRx:
RPx:
ATmega16HVB/32HVB
D
L
RESET
CLR
SET
PORTxn
Q
Q
_
CLR
Q
_
Q
READ PORTx REGISTER
WRITE PORTx REGISTER
READ PINx REGISTER
D
D
PINxn
CLR
Q
_
Q
RRx
WRx
clk
RPx
Figure
I/O
I/O
and SLEEP are com-
”Register Descrip-
14-2, the PINxn
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