ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 18

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.1
8042B–AVR–06/10
Data Memory Access Times
The ATmega16HVB/32HVB is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 1280/2304 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 1K/2K locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 1K/2K bytes of internal data SRAM in the ATmega16HVB/32HVB are all accessible through
all these addressing modes. The Register File is described in
on page
Figure 8-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
12.
Data Memory Map
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
(1K/2K x 8)
0x04FF/0x08FF
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
ATmega16HVB/32HVB
cycles as described in
”General Purpose Register File”
Figure
8-3.
18