ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 17
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8. AVR Memories
8.1
8.2
8.3
8042B–AVR–06/10
Overview
In-System Reprogrammable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATmega16HVB/32HVB. The AVR architec-
ture has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega16HVB/32HVB features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.
The ATmega16HVB/32HVB contains 16K/32K bytes On-chip In-System Reprogrammable Flash
memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-
nized as 8K/16K x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega16HVB/32HVB Program Counter (PC) is 13/14 bits wide, thus addressing the 8K/16K
program memory locations. The operation of Boot Program section and associated Boot Lock
bits for software protection are described in detail in
Self-Programming” on page
description on Flash programming.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 8-1.
Figure 8-2 on page 18
14.
Program Memory Map
shows how the ATmega16HVB/32HVB SRAM Memory is organized.
191.
”Memory Programming” on page 208
Application Flash Section
Boot Flash Section
Program Memory
ATmega16HVB/32HVB
”Boot Loader Support – Read-While-Write
0x0000
0x1FFF/0x3FFF
”Instruction Execution Tim-
contains a detailed
17
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