ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 59

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.2
13.2.3
8042B–AVR–06/10
EIMSK – External Interrupt Mask Register
EIFR – External Interrupt Flag Register
Table 13-1.
Note:
• Bits 7:4 – Reserved
These bits are reserved ins the ATmega16HVB/32HVB, and will always read as zero.
• Bits 3:0 – INT3 – INT0: External Interrupt Request 3:0 Enable
When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Register – EICRA – defines whether the external interrupt is activated
on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt
request even if the pin is enabled as an output. This provides a way of generating a software
interrupt.
• Bits 7:4 – Reserved
These bits are reserved ins the ATmega16HVB/32HVB, and will always read as zero.
• Bits 3:0 – INTF3 – INTF0: External Interrupt Flags 3:0
When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT3:0 are configured as level interrupt. Note that when entering sleep
mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF3:0 flags. See
Enable and Sleep Modes” on page 71
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
ISCn1
0
0
1
1
1. n = 3, 2, 1, or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Interrupt Sense Control
ISCn0
R
R
7
–
0
7
–
0
0
1
0
1
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
for more information.
R
R
4
–
0
4
–
0
INTF3
INT3
ATmega16HVB/32HVB
R/W
R/W
3
0
3
0
INTF2
INT2
R/W
R/W
2
0
2
0
INTF1
INT1
R/W
R/W
1
0
1
0
INTF0
INT0
R/W
R/W
0
0
0
0
”Digital Input
EIMSK
EIFR
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