ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 35

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. Power Management and Sleep Modes
10.1
Table 10-1.
Notes:
8042B–AVR–06/10
Mode
Idle
ADC Noise Reduction
Power-save
Power-off
Sleep Modes
1. Discharge FET must be switched off for Charge Detect to be active.
2. When waking from Power-off the Charger Detect will generate a Power-on Reset (POR). From other sleep modes a charger
detect interrupt will wake-up chip.
Wake-up Sources for Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
Figure 9-1 on page 25
their distribution. The figure is helpful in selecting an appropriate sleep mode. The different sleep
modes and their wake up sources is summarized in
shows a sleep mode state diagram.
To enter any of the sleep modes, the SE bit in SMCR, see
ter” on page
SM2..0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP
instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the register file and
SRAM are unaltered when the device wakes up from any sleep mode except Power-off. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
X
X
X
39, must be written to logic one and a SLEEP instruction must be executed. The
Table 10-3 on page 40
X
X
X
presents the different clock systems in the ATmega16HVB/32HVB, and
X
X
X
X
X
X
for a summary.
X
X
X
Wake-up sources
X
X
ATmega16HVB/32HVB
Table
X
X
X
”SMCR – Sleep Mode Control Regis-
10-1, and
X
X
X
Figure 10-1 on page 36
X
X
X
X
X
X
X
X
X
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