M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 129

BOARD EVAL FOR MC9S08GB60

M68EVB908GB60E

Manufacturer Part Number
M68EVB908GB60E
Description
BOARD EVAL FOR MC9S08GB60
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of M68EVB908GB60E

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S08GB
Data Bus Width
8 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08GB
Kit Contents
GB60 Evaluation Kit
Rohs Compliant
Yes
For Use With/related Products
MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
V — Two’s Complement Overflow Flag
H — Half-Carry Flag
I — Interrupt Mask Bit
N — Negative Flag
Z — Zero Flag
C — Carry/Borrow Flag
Freescale Semiconductor
The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C condition code bits to automatically add a correction value to the result from a previous ADD or
ADC on BCD operands to correct the result to a valid BCD value.
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the
interrupt service routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or
TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the
possibility of an intervening interrupt, provided I was set.
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00 or $0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set
if the loaded or stored value was all 0s.
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
1 = Interrupts disabled
0 = Interrupts enabled
1 = Negative result
0 = Non-negative result
1 = Zero result
0 = Non-zero result
1 = Carry out of bit 7
0 = No carry out of bit 7
MC9S08GB/GT Data Sheet, Rev. 2.3
Programmer’s Model and CPU Registers
129

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