M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 14

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section Number
13.1 Introduction ...................................................................................................................................205
13.2 Functional Description ..................................................................................................................207
13.3 Resets ............................................................................................................................................210
13.4 Interrupts .......................................................................................................................................211
13.5 IIC Registers and Control Bits ......................................................................................................212
14.1 Introduction ...................................................................................................................................221
14.2 Signal Description .........................................................................................................................222
14
13.1.1 Features ..........................................................................................................................205
13.1.2 Modes of Operation .......................................................................................................205
13.1.3 Block Diagram ...............................................................................................................206
13.1.4 Detailed Signal Descriptions .........................................................................................206
13.2.1 IIC Protocol ...................................................................................................................207
13.4.1 Byte Transfer Interrupt ..................................................................................................211
13.4.2 Address Detect Interrupt ................................................................................................211
13.4.3 Arbitration Lost Interrupt ..............................................................................................211
13.5.1 IIC Address Register (IIC1A) ........................................................................................212
13.5.2 IIC Frequency Divider Register (IIC1F) ........................................................................212
13.5.3 IIC Control Register (IIC1C) .........................................................................................215
13.5.4 IIC Status Register (IIC1S) ............................................................................................216
13.5.5 IIC Data I/O Register (IIC1D) .......................................................................................217
14.1.1 Features ..........................................................................................................................221
14.1.2 Modes of Operation .......................................................................................................221
14.1.3 Block Diagram ...............................................................................................................221
14.2.1 Overview ........................................................................................................................222
13.1.4.1 SCL1 — Serial Clock Line ...........................................................................206
13.1.4.2 SDA1 — Serial Data Line ............................................................................206
13.2.1.1 START Signal ...............................................................................................208
13.2.1.2 Slave Address Transmission .........................................................................208
13.2.1.3 Data Transfer .................................................................................................208
13.2.1.4 STOP Signal ..................................................................................................209
13.2.1.5 Repeated START Signal ...............................................................................209
13.2.1.6 Arbitration Procedure ....................................................................................209
13.2.1.7 Clock Synchronization ..................................................................................209
13.2.1.8 Handshaking .................................................................................................210
13.2.1.9 Clock Stretching ............................................................................................210
14.1.2.1 Stop Mode .....................................................................................................221
14.1.2.2 Power Down Mode .......................................................................................221
14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................223
Analog-to-Digital Converter (ATD) Module
Inter-Integrated Circuit (IIC) Module
MC9S08GB/GT Data Sheet, Rev. 2.3
Chapter 13
Chapter 14
Title
Freescale Semiconductor
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