M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 55

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.2
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5
through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning
or effect. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory
as usual and then issue a new MCU reset.
KEYEN — Backdoor Key Mechanism Enable
FNORED — Vector Redirection Disable
Freescale Semiconductor
When this bit is 0, the backdoor key mechanism cannot be used to disengage security. The backdoor
key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to
write key comparison values that would unlock the backdoor key. For more detailed information about
the backdoor key mechanism, refer to
When this bit is 1, vector redirection is disabled.
1 = If user firmware writes an 8-byte value that matches the nonvolatile backdoor key
0 = No backdoor key access allowed.
1 = Vector redirection disabled.
0 = Vector redirection enabled.
FLASH Options Register (FOPT and NVOPT)
(NVBACKKEY through NVBACKKEY+7, in that order), security is temporarily disengaged
until the next MCU reset.
200 kHz
150 kHz
20 MHz
10 MHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
Reset:
Read:
Write:
(Binary)
PRDIV8
1
0
0
0
0
0
0
0
KEYEN
Bit 7
Figure 4-5. FLASH Options Register (FOPT)
Table 4-6. FLASH Clock Divider Settings
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
DIV5:DIV0
(Decimal)
FNORED
This register is loaded from nonvolatile location NVOPT during reset.
12
49
39
19
6
9
4
0
0
Section 4.5,
0
5
192.3 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
f
FCLK
“Security.”
0
4
Program/Erase Timing Pulse
(5 µs Min, 6.7 µs Max)
0
3
5.2 µs
6.7 µs
5 µs
5 µs
5 µs
5 µs
5 µs
5 µs
0
2
FLASH Registers and Control Bits
SEC01
1
SEC00
Bit 0
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