M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 140

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Central Processor Unit (CPU)
140
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
Source
Form
Load Accumulator from
Memory
Load Index Register (H:X)
from Memory
Load X (Index Register
Low) from Memory
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate
(Two’s Complement)
No Operation
Nibble Swap
Accumulator
Inclusive OR Accumulator
and Memory
Push Accumulator onto
Stack
Push H (Index Register
High) onto Stack
Push X (Index Register
Low) onto Stack
Operation
Table 8-1. HCS08 Instruction Set Summary (Sheet 5 of 7)
MC9S08GB/GT Data Sheet, Rev. 2.3
Push (A); SP ← (SP) – $0001
Push (H); SP ← (SP) – $0001
Push (X); SP ← (SP) – $0001
IX+/DIR and DIR/IX+ Modes
0
C
(M)
H:X ← (H:X) + $0001 in
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
H:X ← (M:M + $0001)
A ← – (A) = $00 – (A)
X ← – (X) = $00 – (X)
A ← (A[3:0]:A[7:4])
destination
Uses 1 Bus Cycle
b7
b7
X:A ← (X) × (A)
Description
A ← (A) | (M)
A ← (M)
X ← (M)
← (M)
b0
b0
source
C
0
V H I N Z C
0 – –
0 – –
0 – –
0 – –
– 0 – – – 0 INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– –
– – 0
– –
on CCR
Effect
–
–
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX
IX2
IX1
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
Freescale Semiconductor
9ECE
9EDE
9EDA
9EAE
9EBE
9EEE
9EEA
9ED6
9EE6
9EFE
9E68
9E64
9E60
AE
BE
CE
DE
EE
AA
BA
CA
DA
EA
C6
D6
FE
9D
FA
A6
B6
E6
4E
5E
6E
7E
8B
F6
45
55
32
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
62
87
89
ii
dd
hh ll
ee ff
ff
ee ff
ff
jj
dd
hh ll
ee ff
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
kk
2
3
4
4
3
3
5
4
3
4
5
5
6
5
5
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
5
5
4
5
5
5
1
1
5
4
6
1
1
2
3
4
4
3
3
5
4
2
2
2