M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 85

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PTADn — Port A Data Register Bit n (n = 0–7)
PTAPEn — Pullup Enable for Port A Bit n (n = 0–7)
Freescale Semiconductor
For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port A pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled provided the corresponding PTADDn is 0. For port A pins that are configured as outputs,
these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of port
A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable
bits enable pulldown rather than pullup devices.
PTAD
PTAPE
PTASE
PTADD
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTAPE7
PTASE7
PTADD7
PTAD7
Bit 7
0
0
0
0
PTAPE6
PTASE6
PTADD6
MC9S08GB/GT Data Sheet, Rev. 2.3
PTAD6
Figure 6-9. Port A Registers
6
0
0
0
0
PTADD5
PTAPE5
PTASE5
PTAD5
5
0
0
0
0
PTADD4
PTAPE4
PTASE4
PTAD4
4
0
0
0
0
PTADD3
PTAPE3
PTASE3
PTAD3
3
0
0
0
0
PTADD2
PTAPE2
PTASE2
PTAD2
Parallel I/O Registers and Control Bits
2
0
0
0
0
PTADD1
PTAPE1
PTASE1
PTAD1
1
0
0
0
0
PTADD0
PTAPE0
PTASE0
PTAD0
Bit 0
0
0
0
0
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