M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 182

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communications Interface (SCI) Module
TC — Transmission Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Flag
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TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being
transmitted.
TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following:
RDRF becomes set when a character transfers from the receive shifter into the receive data register
(SCIxD). In 8-bit mode, to clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data
register (SCIxD). In 9-bit mode, to clear RDRF, read SCIxS1 with RDRF = 1 and then read SCIxD
and the SCI control 3 register (SCIxC3). SCIxD and SCIxC3 can be read in any order, but the flag is
cleared only after both data registers are read.
IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity.
When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character
is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or
11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When
ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any
logic high bit times at the end of the previous character do not count toward the full character time of
logic high needed for the receiver to detect an idle line.
To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE
has been cleared, it cannot become set again until after a new character has been received and RDRF
has been set. IDLE will be set only once even if the receive line remains idle for an extended period.
1 = Transmitter idle (transmission activity complete).
0 = Transmitter active (sending data, a preamble, or a break).
1 = Receive data register full.
0 = Receive data register empty.
1 = Idle line was detected.
0 = No idle line detected.
— Write to the SCI data register (SCIxD) to transmit new data
— Queue a preamble by changing TE from 0 to 1
— Queue a break character by writing 1 to SBK in SCIxC2
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor