M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 250

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
15.5.1.1 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
ENBDM — Enable BDM (Permit Active Background Mode)
BDMACT — Background Mode Active Status
BKPTEN — BDC Breakpoint Enable
FTS — Force/Tag Select
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Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or
whenever the debug host resets the target and remains 1 until a normal reset clears it.
This is a read-only status bit.
If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and
BDCBKPT match register are ignored.
When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT
match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction
queue, the CPU enters active background mode rather than executing the tagged opcode.
1 = BDM can be made active to allow active background mode commands.
0 = BDM cannot be made active (non-intrusive commands still allowed).
1 = BDM active and waiting for serial commands.
0 = BDM not active (user application program running).
1 = BDC breakpoint enabled.
0 = BDC breakpoint disabled.
1 = Breakpoint match forces active background mode at next instruction boundary (address need
0 = Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute
Reset in Active BDM:
not be an opcode).
that instruction.
Normal Reset:
Read:
Write:
Figure 15-5. BDC Status and Control Register (BDCSCR)
ENBDM
Bit 7
0
1
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
BDMACT
6
0
1
BKPTEN
5
0
0
FTS
4
0
0
CLKSW
3
0
1
WS
2
0
0
Freescale Semiconductor
WSF
1
0
0
Bit 0
DVF
0
0