M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 240

BOARD EVAL FOR MC9S08GB60

M68EVB908GB60E

Manufacturer Part Number
M68EVB908GB60E
Description
BOARD EVAL FOR MC9S08GB60
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of M68EVB908GB60E

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S08GB
Data Bus Width
8 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08GB
Kit Contents
GB60 Evaluation Kit
Rohs Compliant
Yes
For Use With/related Products
MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Development Support
Figure 15-3
shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
BDC CLOCK
(TARGET MCU)
HOST DRIVE
HIGH-IMPEDANCE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED START
OF BIT TIME
R-C RISE
BKGD PIN
10 CYCLES
EARLIEST START
OF NEXT BIT
10 CYCLES
HOST SAMPLES BKGD PIN
Figure 15-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
MC9S08GB/GT Data Sheet, Rev. 2.3
240
Freescale Semiconductor

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