YR0K42378FC000BA Renesas Electronics America, YR0K42378FC000BA Datasheet - Page 202
YR0K42378FC000BA
Manufacturer Part Number
YR0K42378FC000BA
Description
KIT EVAL FOR H8S/2378
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of YR0K42378FC000BA
Contents
Board
For Use With/related Products
H8S/2378
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 202 of 1208
- Download datasheet (8Mb)
Section 5 Interrupt Controller
5.7
5.7.1
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above conflict will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Rev.7.00 Mar. 18, 2009 page 134 of 1136
REJ09B0109-0700
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Usage Notes
Conflict between Interrupt Generation and Disabling
φ
Figure 5.6 Conflict between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
TCIV exception handling
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