YR0K42378FC000BA Renesas Electronics America, YR0K42378FC000BA Datasheet - Page 398

• Manufacturer Part Number: YR0K42378FC000BA
• Description: KIT EVAL FOR H8S/2378
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of YR0K42378FC000BA

• Contents: Board
• For Use With/related Products: H8S/2378
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 7 DMA Controller (DMAC)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
Figure 7.16 shows an example of the setting procedure for block transfer mode.
Rev.7.00 Mar. 18, 2009 page 330 of 1136
REJ09B0109-0700
and transfer destination
Set number of transfers
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
Figure 7.16 Example of Block Transfer Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address in MARA, and
[3] Set the block size in both ETCRAH and
[4] Set each bit in DMACRA and DMACRB.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Set the FAE bit to 1 to select full address
• Specify enabling or disabling of internal
the transfer destination address in MARB.
ETCRAL. Set the number of transfers in
ETCRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
• Set the BLKE bit to 1 to select block transfer
• Specify whether the transfer source or the
• Specify whether MARB is to be incremented,
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
• Set both the DTME bit and the DTE bit to 1 to
mode.
interrupt clearing with the DTA bit.
decremented, or fixed, with the SAID and
SAIDE bits.
mode.
transfer destination is a block area with the
BLKDIR bit.
decremented, or fixed, with the DAID and
DAIDE bits.
DTF0.
interrupts to the CPU with the DTIE bit.
enable transfer.