YR0K42378FC000BA Renesas Electronics America, YR0K42378FC000BA Datasheet - Page 299

Manufacturer Part Number

YR0K42378FC000BA

KIT EVAL FOR H8S/2378

Manufacturer

Renesas Electronics America

For Use With/related Products

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Section 6 Bus Controller (BSC)

Burst Operation

With synchronous DRAM, in addition to full access (normal access) in which data is accessed by

outputting a row address for each access, burst access is also provided which can be used when

making consecutive accesses to the same row address. This access enables fast access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal

cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following

column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE

bit to 1 when synchronous DRAM of CAS latency 1 is connected.

Burst Access Operation Timing: Figure 6.52 shows the operation timing for burst access. When

there are consecutive access cycles for continuous synchronous DRAM space, the column address

output cycles continue as long as the row address is the same for consecutive access cycles. The

row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.

Rev.7.00 Mar. 18, 2009 page 231 of 1136

REJ09B0109-0700