YR0K42378FC000BA Renesas Electronics America, YR0K42378FC000BA Datasheet - Page 423

Manufacturer Part Number

YR0K42378FC000BA

KIT EVAL FOR H8S/2378

Manufacturer

Renesas Electronics America

For Use With/related Products

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state

is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is

enabled. This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/break interrupt (DTE = 0 and DTIE = 1)

• TEND pin enable (TEE = 1)

• DACK pin enable (FAE = 0 and SAE = 1)

DMA internal

DMA register

Figure 7.40 Contention between DMAC Register Update and CPU Read

Note: The lower word of MAR is the updated value after the operation in [1].

CPU longword read

Rev.7.00 Mar. 18, 2009 page 355 of 1136

DMA transfer cycle

Section 7 DMA Controller (DMAC)

REJ09B0109-0700