M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 100

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 76 of 587
Figure 8.9
8.2.4.1
The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not.
Address output or data output is held during the recovery cycle (only when using the separate bus). Devices,
which require longer address hold time or data hold time, are connectable.
- Recovery cycle when separate bus is selected (
- Recovery cycle when multiplexed bus is selected (
A: address
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the
Bus Cycle with Recovery Cycle Inserted
Recovery Cycle
LA: Latch address
WR, WRL, WRH
WR (WRL)
Read data
Read data
Write data
Write data
Address
BCLK
BCLK
ALE
CSi
CSi
RD
RD
RD: Read data
LA
LA
WD: Write data
A
WD
RD
bus cycle is 1
bus cycle is 2
WD
Recovery cycle
(Note 1)
RD
Address is held
Data is held
φ
CSi
+ 2
φ
pin keeps outputting "L".
+ 3
φ
)
Recovery cycle
(Note 1)
φ
)
Data is held
8. Bus