M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 88

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 64 of 587
8.1.1
8.1.2
8.1.3
Table 8.2
NOTE:
00b
(multiplexed bus not used)
01b
(access the CS2 area
using multiplexed bus)
10b
(access the CS1 area
using multiplexed bus)
11b
(access the all CS areas
using multiplexed bus)
8.1.3.1
8.1.3.2
1. In microprocessor mode, do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using
The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space
(CS area) vary in each external space mode. Bits PM11 and PM10 in the PM1 register select external space
mode.
The DS register selects either external 8-bit data bus or 16-bit data bus per each external space. The data bus in
the external space 3 becomes 16 bits wide when a low-level (“L”) signal is applied to the BYTE pin after reset,
and 8 bits wide when a high-level (“H”) signal is applied. Do not change the BYTE pin level while the MCU is
operating. Internal bus is always 16 bits wide.
Bits PM05 and PM04 in the PM0 register select either the separate bus or multiplexed bus. The MCU starts up
with the separate bus after reset.
With the separate bus format, the MCU performs data input/output and address output using individual buses.
The DS register selects 8-bit or 16-bit external data bus for each external space. If all DSi bits in the DS register
(i = 0 to 3) are set to 0 (8-bit data bus), port P0 functions as the data bus and port P1 as the programmable I/O
port.
If any of the DSi bits is set to 1 (16-bit data bus), ports P0 and P1 function as the data bus. Port P1 output is
undefined when the MCU accesses the space where its DSi bit is set to 0.
With the multiplexed bus format, the MCU performs data input/output and address output using the same bus
by time-sharing. D0 to D7 are time-multiplexed with A0 to A7 in the space accessed by the 8-bit data bus. D0 to
D15 are time-multiplexed with A0 to A15 in the space accessed by the 16-bit data bus.
When bits PM05 and PM04 in the PM0 register are set to 11b (access all CS area using multiplexed bus),
address bus has only 16 bits using A0 to A15. In this case, the accessible space is 64 Kbytes per each chip-select
output. Refer to Table 8.3 Processor Mode and Pin Function for details.
Table 8.2 lists multiplexed bus settings and chip-select areas.
PM05 and PM04
multiplexed bus).
bits setting
Selecting External Address Bus
Selecting External Data Bus
Selecting Separate Bus/Multiplexed Bus
Separate Bus
Multiplexed Bus
Multiplexed Bus Settings and Chip-Select Areas
(1)
(external space
Do not set to
these values
mode 0
00b
(external space
mode 1)
PM11 and PM10 Bits Setting
CS2
CS1
CS0
CS1
CS2
01b
Separate bus
(external space
Do not set to
this value
mode 2)
CS1
CS0
CS1
10b
(external space
mode 3)
CS2
CS1
CS0
CS1
CS2
CS3
11b
8. Bus