M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 93

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 69 of 587
Figure 8.3
8.2.4
External Space Wait Control Register i (i = 0 to 3)
b7 b6 b5 b4
Software wait states for the internal ROM and internal RAM can be set using the PM12 bit in the PM1 register,
for the SFR area using the PM13 bit, and for external spaces using the EWCRi register (i = 0 to 3). Table 8.6
lists a software wait state and bus cycle.
The basic bus cycle for the internal ROM, internal RAM, and SFR area is one bus clock (BCLK) cycle. A read
from the internal ROM takes the basic bus cycle. A read or write to the internal RAM takes the basic bus cycle.
When the PM12 bit in the PM1 register to 1 (1 wait state), an access to the internal ROM or internal RAM takes
two BCLK cycles.
A read or write to the SFR area takes two BCLK cycles (1 wait state). When the PM13 bit in the PM1 register is
set to 1 (2 wait states), an access takes three BCLK cycles.
The external bus cycle is divided into two phases: the number of BCLK cycles in the period from the beginning
of the bus access until the read or write output signal becomes “L” (first φ), and the number of BCLK cycles in
the period from the read or write output signal becomes “L” until the signal changes to “H” (second φ).
The minimum read or write cycle for the external bus is two BCLK cycles (1 φ + 1 φ). The EWCRi register (i =
0 to 3) selects an external bus cycle from 12 types for the separate bus and seven types for the multiplexed bus.
For example, when bits EWCRi4 to EWCRi0 in the EWCRi register are set to 00011b (1 φ + 3 φ), the external
bus cycle is four BCLK cycles.
Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show external bus timings.
NOTES:
1. The number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L".
2. The number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H".
Bus Timing
b3
b2
EWCR0 to EWCR3 Registers
b1
b0
Bit Symbol
EWCRi0
EWCRi1
EWCRi2
EWCRi3
EWCRi4
EWCRi6
Symbol
EWCR0 to EWCR3
(b5)
(b7)
−
−
Bus cycle select bits
Unimplemented.
Write 0. Read as undefined value.
Recovery cycle insert
select bit
Unimplemented.
Write 0. Read as undefined value.
Bit Name
(3)
0048h, 0049h, 004Ah, 004Bh
Address
b4 b3 b2 b1 b0 (1)
0 0 0 0 1: 1 φ + 1 φ
0 0 0 1 0: 1 φ + 2 φ
0 0 0 1 1: 1 φ + 3 φ
0 0 1 0 0: 1 φ + 4 φ
0 0 1 0 1: 1 φ + 5 φ
0 0 1 1 0: 1 φ + 6 φ
0 1 0 1 0: 2 φ + 2 φ
0 1 0 1 1: 2 φ + 3 φ
0 1 1 0 0: 2 φ + 4 φ
0 1 1 0 1: 2 φ + 5 φ
1 0 0 1 1: 3 φ + 3 φ
1 0 1 0 0: 3 φ + 4 φ
1 0 1 0 1: 3 φ + 5 φ
1 0 1 1 0: 3 φ + 6 φ
Do not set to values other than the above
0: Insert no recovery cycle when accessing
1: Insert a recovery cycle when accessing
external space i
external space i
(2)
Function
After Reset
X0X0 0011b
RW
RW
RW
RW
RW
RW
RW
−
−
8. Bus