M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 520

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 496 of 587
Figure 26.2
Figure 26.3
ROM Code Protect Control Address
b7
b6 b5 b4
1
NOTES:
1
1. When the ROM code protect is enabled by setting the ROMCP1 bits to values other than 11b, the flash memory is protected
2. Set the bits 5 to 0 to 111111b when the ROMCP1 bits are set to other than 11b.
3. To disable the ROM code protect, erase the block including the ROMCP address in standard serial I/O mode or CPU rewrite
4. The ROMCP address is set to FFh when the block including the ROMCP address is erased.
5. When the ROMCP address is set to 00h or FFh, the ROM code protect function is disabled.
b3
1
against reading or rewriting the contents in parallel I/O mode.
mode.
b2
ROMCP Address
Addresses for Stored ID Codes
1
b1
1
b0
1
FFFFDFh to FFFFDCh
FFFFEBh to FFFFE8h
FFFFEFh to FFFFECh
FFFFE3h to FFFFE0h
FFFFE7h to FFFFE4h
FFFFF3h to FFFFF0h
FFFFF7h to FFFFF4h
FFFFFBh to FFFFF8h
FFFFFFh to FFFFFCh
Bit Symbol
ROMCP1
Address
(b5-b0)
Symbol
ROMCP
−
Reserved bits
ROM code protect
set bits
(1)(2)(3)
Bit Name
ROMCP
ID1
ID2
ID3
ID4
ID5
ID6
ID7
(5)
Address
FFFFFFh
Overflow Vector
Address Match Vector
Undefined Instruction Vector
Watchdog Timer Vector
BRK Instruction Vector
NMI Vector
Reset Vector
Set to 1 to use ROM protect function
b7 b6
0 0: ROM code protect enabled
0 1: ROM code protect enabled
1 0: ROM code protect enabled
1 1: ROM code protect disabled
4 bytes
Function
Factory setting
FFh
(4)
26. Flash Memory
RW
RW
RW