M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 314

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 290 of 587
Figure 17.53
j = 0 when i = 5, j = 9 when i = 6
The above applies under the following conditions:
NOTES:
Example of the receive operation timing (1 stop bit)
RXDi input
Clock divided by UiBRG
register
Internal receive clock
UiRR bit in the IIOjIR
register
RI bit in the UiC1 register
RTSi output
- UiMR register: STPS bit = 0 (1 stop bit)
- UiC0 register: CRS bit = 1 (CTS function not used)
1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive
2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled.
clock is generated after detecting the falling edge of the start bit, and then the receive operation starts.
When the receive operatin is cancelled, the RTSi output becomes "L".
Receive Operation in UART Mode
“H”
“L”
1
0
1
0
“H”
“L”
The output signal becomes "L"
when the RE bit in the UiC1 register
is set to 1
(note 1)
The output signal becomes "H"
when the receive operation starts
Start bit
Verify the level
(note 2)
D0
Input the
receive data
17. Serial Interfaces (UART5 and UART6)
This bit becomes 1 when the data is transferred
from UARTi receive shift register to UiRB register
The RI bit becomes 0 and RTSi output
becomes "L" by reading the UiRB register
Set to 0 by an interrupt request
acknowledgement or by a program
Stop bit