M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 112

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 88 of 587
Figure 9.8
Count Source Prescaler Register
Clock Prescaler Reset Register
b7 b6 b5 b4
b7 b6 b5 b4
NOTES:
1. Set bits CNT3 to CNT0 after the CST bit is set to 0.
2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.
b3
b3
b2
b2
TCSPR Register, CPSRF Register
b1
b1
b0
b0
Bit Symbol
Bit Symbol
(b6-b4)
(b6-b0)
CPSR
CNT0
CNT1
CNT2
CNT3
CST
CPSRF
Symbol
Symbol
TCSPR
−
−
Division rate select bits
Reserved bits
Operation enable bit
Unimplemented.
Write 0. Read as undefined value.
Clock prescaler reset bit
Bit Name
Bit Name
(1)
Address
0341h
Address
035Fh
If the setting value is n, f2n is the main clock,
on-chip oscillator clock, or PLL clock divided
by 2n.
When n is set to 0, no division is selected
Read as undefined value
0: Divider stops
1: Divider operates
When the CPSR bit is set to 1, a divider for
fC32 is reset. Read as 0.
Function
Function
9. Clock Generation Circuits
0XXX XXXXb
After Reset
After Reset
0XXX 0000b
(2)
RW
RW
RW
RW
RW
RW
RW
RW
−
−