M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 399

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 375 of 587
Figure 22.43
Group i SI/O Special Communication Interrupt Determination Register (i=0,1)
b7
b6 b5 b4
NOTES:
1. Set to 00b except in HDLC data processing mode.
2. The SRTiR bit in the IIO4IR register is set to 1, if any of bits IRF3 to IRF0 is set to 1.
b3
0
b2
G0IRF and G1IRF Registers
0
b1
0
b0
0
Bit Symbol
(b3-b0)
IRF0
IRF1
IRF2
IRF3
Symbol
G0IRF
G1IRF
−
Reserved bits
Interrupt source determination
flag 0
Interrupt source determination
flag 1
Interrupt source determination
flag 2
Interrupt source determination
flag 3
Bit Name
Address
00FEh
013Eh
Set to 0
0 : The GiDR register (receive data register)
1 : The GiDR register matches the GiCMP0
0 : The GiDR register (receive data register)
1 : The GiDR register matches the GiCMP1
0 : The GiDR register (receive data register)
1 : The GiDR register matches the GiCMP2
0 : The GiDR register (receive data register)
1 : The GiDR register matches the GiCMP3
does not match the GiCMP0 register
register
does not match the G0CMP1 register
register
does not match the GiCMP2 register
register
does not match the GiCMP3 register
register
Function
After Reset
0000 XXXXb
0000 XXXXb
RW
RW
RW
RW
RW
RW
(1)( 2)