Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 116

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
DEMODULATION Mode
In DEMODULATION mode, the timer begins counting on the first external Timer Input
transition. The desired transition (rising edge or falling edge or both) is set by the TPOL
bit in the Timer Control 1 register and TPOLHI bit in the Timer Control 2 register. The
Timer counts timer clocks up to the 16-bit Reload value.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM0 High and Low Byte
Registers for rising input edges of the timer input signal. For falling edges the capture
count value is written to the Timer PWM1 High and Low Byte Registers. The TPOL bit in
the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling
edge of the Timer Input signal. If the TPOLHI bit in the Timer Control 2 register is set,
Capture is done on both the rising and falling edges of the input signal.
Whenever the Capture event occurs, an interrupt is generated and the timer continues
counting. The corresponding event flag bit PWMxEF in Timer Status register is set to
indicate the timer interrupt is due to an input Capture event.
The timer counts up to the 16-bit Compare value stored in the Timer Reload High and
Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the
count value in the Timer High and Low Byte registers is reset to
resumes. The RTOEF event flag bit in Timer Status register is set to indicate the timer
interrupt is due to a Reload event. Software can use this bit to determine if a reload
occurred prior to a Capture.
Follow the steps below for configuring a timer for DEMODULATION mode and initiating
the count:
1. Write to the Timer Control 1 register to:
2. Write to the Timer Control 2 register to:
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
4. Write to the Timer High and Low Byte registers to set the starting count value
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
–
–
–
–
–
–
TICONFIG.
(typically
Disable the timer.
Configure the timer for DEMODULATION mode. Setting the mode also involves
writing to TMODEHI bit in TxCTL0 register.
Set the prescale value.
Set TPOL bit to set the Capture edge (rising or falling) for the Timer Input. This
applies only if TPOLHI bit in TxCTL2 register is not set.
Choose the timer clock source
Set the TPOLHI bit if the Capture is required on both edges of the input signal
0001H
).
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
0001H
and counting
®
F1680 Series
Timers
102