Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 242

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Slave Transactions
15. After the I
16. The I
17. The I
18. The I
19. The I
20. The I
21. The I
22. The software responds by reading the I
23. The I
24. If there are more bytes to transfer, the I
25. The I
26. The software responds by setting the
27. A
The following sections describe Read and Write transactions to the I
configured for 7-bit and 10-bit Slave modes.
Slave Address Recognition
The following Slave address recognition options are supported:
transfer), the I
the next High period of SCL.
If the slave does not acknowledge the address byte, the I
NCKI bit in the I
the I
setting the
Data Register, sends the
bits. The transaction is complete, and the following steps can be ignored.
Register (the third address transfer).
slave read address and a 1 (Read).
next High period of SCL.
is to be the final byte, the software must set the
based on the value of the
Register).
STOP
2
2
2
2
2
2
2
2
2
C State Register. The software responds to the Not Acknowledge interrupt by
C controller sends a repeated
C controller loads the I
C controller sends
C slave sends an Acknowledge by pulling the SDA signal Low during the 
C controller shifts in a byte of data from the slave.
C controller asserts the Receive interrupt.
C controller sends an Acknowledge or Not Acknowledge to the I
C controller generates a NAK interrupt (the
condition is sent to the I
2
STOP
C controller shifts out the address bits listed in
2
C slave sends an Acknowledge by pulling the SDA signal Low during
2
bit and clearing the
C Status Register, sets the
P R E L I M I N A R Y
STOP
11110b
NAK
2
bit.
C Shift Register with the contents of the I
condition on the bus, and clears the
2
, followed by the two most-significant bits of the
C Slave.
START
TXI
STOP
2
2
C Data Register. If the next data byte
C controller returns to
bit. The I
condition.
bit of the I
ACKV
NAK
bit, and clears the
NCKI
2
Z8 Encore! XP
C controller flushes the Transmit
bit of the I
2
C Control Register.
2
bit in the I2CISTAT
C controller sets the 
Step 9
Product Specification
I2C Master/Slave Controller
2
Step
C Control Register.
2
C controller
(the second address
STOP
18.
®
ACK
F1680 Series
2
2
C Slave, 
and
C Data
bit in 
NCKI
228