Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 140

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Multi-Channel Timer Control Register Definitions
PS025011-1010
Multi-Channel Timer Address Map
Table 66
address space, sub-address is used for Timer Control 0 register, Timer Control 1 register,
Channel Status 0 register, Channel Status 1 register, Channel-y Control register, 
Channel-y High, and Low byte register. Only Timer High and Low byte register and
Reload High and Low byte register can be directly accessed.
While writing a subregister, first write sub-address to Timer Sub-Address Register, then
write data to subregister0, subregister1, or subregister2. Read is the same as Write.
Table 66. Multi-Channel Timer Address Map
Address/Sub-address
Direct Access Register
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
Subregister 0
0
1
2
3
4
5
Subregister 1
0
1
2
3
4
5
defines the byte address offsets for the Multi-channel Timer registers. For saving
P R E L I M I N A R Y
Register/Subregister Name
Timer (Counter) High
Timer (Counter) Low
Timer Reload High
Timer Reload Low
Timer Sub-Address
SubRegister 0
SubRegister 1
SubRegister 2
Timer Control 0
Channel Status 0
Channel A Capture/Compare High
Channel B Capture/Compare High
Channel C Capture/Compare High
Channel D Capture/Compare High
Timer Control 1
Channel Status 1
Channel A Capture/Compare Low
Channel B Capture/Compare Low
Channel C Capture/Compare Low
Channel D Capture/Compare High
Z8 Encore! XP
Product Specification
Multi-Channel Timer
®
F1680 Series
126