Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 229

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

I
PS025011-1010
2
C Master/Slave Controller
Architecture
The I
bus-compatible with the I
and a serial clock signal (SCL) bidirectional lines. The features of I
•
•
•
•
•
•
•
•
•
Figure 42
Operates in MASTER/SLAVE or SLAVE ONLY modes.
Supports arbitration in a multimaster environment (MASTER/SLAVE mode).
Supports data rates up to 400 Kbps.
7-bit or 10-bit slave address recognition (interrupt only on address match).
Optional general call address recognition.
Optional digital filter on receive SDA, SCL lines.
Optional interactive receive mode allows software interpretation of each received
address and/or data byte before acknowledging.
Unrestricted number of data bytes per transfer.
Baud Rate Generator can be used as a general-purpose timer with an interrupt, if the
I
2
2
C controller is disabled.
C Master/Slave Controller ensures that the Z8 Encore! XP F1680 Series devices are
on page 216 displays the architecture of the I
2
C protocol. The I
P R E L I M I N A R Y
2
C bus consists of the serial data signal (SDA)
2
Z8 Encore! XP
C controller.
Product Specification
I2C Master/Slave Controller
2
C controller include:
®
F1680 Series
215