Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 236

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
S
Address
Slave
the
byte is being sent).
Master Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate the data that is
transferred from the Master to the Slave, and the unshaded regions indicate the data 
that is transferred from the Slave to the Master. The transaction field labels are 
defined as follows:
Master Write Transaction with a 7-Bit Address
Figure 43
Figure 43. Data Transfer Format—Master Write Transaction with a 7-Bit Address
Follow the steps below for a Master transmit operation to a 7-bit addressed slave:
1. The software initializes the
2. The software asserts the
3. The I
4. The software responds to the TDRE bit by writing a 7-bit slave address plus the 
5. The software sets the
6. The I
S
W
A
A
P
STOP
MASTER/SLAVE mode with either a 7-bit or 10-bit slave address. The
selects the address width for this mode when addressed as a slave (but not 
for the remote slave). The software asserts the IEN bit in the I
interrupts.
Write bit (which is cleared to 0) to the I
W = 0
2
2
bit after the second TDRE interrupt (which indicates that the second address
displays the data transfer format from a Master to a 7-bit addressed slave.
C interrupt asserts, because the I
C controller sends a
Start
Write
Acknowledge
Not Acknowledge
Stop
A
START
Data
P R E L I M I N A R Y
TXI
START
MODE
bit of the I
bit of the I
A
field in the I
condition to the I
2
2
2
C Data Register is empty.
2
C Data Register.
C Control Register.
C Control Register to enable transmit
Data
2
C Mode Register for 
2
Z8 Encore! XP
A
C slave.
Product Specification
Data
I2C Master/Slave Controller
2
C Control Register.
®
F1680 Series
A/A
MODE
field
P/S
222