Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 118

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Table 51. DEMODULATION Mode Initialization Example (Continued)
Register
T0PWM1H
T0PWM1H
T0NFC
PAADDR
PACTL[1:0]
IRQ0ENH[5]
IRQ0ENL[5]
T0CTL1
Notes: After receiving the input trigger (rising or falling edge), Timer 0 will:
Reading the Timer Count Values
Timer Output Signal Operation
Timer Noise Filter
1. Start counting on timer clock.
2. Upon receiving a Timer 0 Input rising edge, save Capture value in T0PWM0 
3. Upon receiving a Timer 0 Input falling edge, save Capture value in T0PWM1 registers, 
4. After timer count to ABCD clocks, set reload event flag, and reset Timer count to start value.
registers, generate interrupt, and continue to count.
generate interrupt, and continue to count.
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte
register is read, the contents of the Timer Low Byte register are placed in a holding
register. A subsequent read from the Timer Low Byte register returns the value in the
holding register. This operation allows accurate reads of the full 16-bit timer count value
while enabled. When the timers are not enabled, a read from the Timer Low Byte register
returns the actual value in the counter.
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
A Noise Filter circuit is included which filters noise on a Timer Input signal before the
data is sampled by the block.
C0H
Value
00H
00H
02H
11B
0B
0B
84H
Comment
Initial PWM1 value = 0000H
NFEN = 1 enables noise filter
NFCTL = 100B enables 8-bit up/down counter
Selects Port A Alternate Function control register.
PACTL[0] enables Timer 0 Input alternate function.
PACTL[1] enables Timer 0 Output alternate function.
Disables the Timer 0 interrupt.
TEN = 1 enables the timer. All other bits left in desired settings.
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
Timers
104