Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 238

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
S
Slave Address
1st Byte
Figure 44. Data Transfer Format—Master Write Transaction with a 10-Bit Address
The first 7 bits transmitted in the first byte are
significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
Follow the steps below for a master transmit operation to a 10-bit addressed slave:
1. The software initializes the
2. The software asserts the
3. The I
4. The software responds to the TDRE interrupt by writing the first Slave Address byte
5. The software asserts the
6. The I
7. The I
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
9. The software responds by writing the second byte of address into the contents 
10. The I
11. The I
MASTER/SLAVE mode with 7- or 10-bit addressing (the I
mixing of slave address types). The
when addressed as a slave (but not for the remote slave). The software asserts the IEN
bit in the I
interrupts.
(
I
asserts.
of the I
the Write bit out via the SDA signal.
high period of SCL. The I
If the slave does not acknowledge the first address byte, the I
the NCKI bit in the I
the I
setting the
address byte from the data register, sends a
11110xx0
2
C Data Register.
2
2
2
2
2
2
C State Register. The software responds to the Not Acknowledge interrupt by
C interrupt asserts because the I
C controller sends a
C controller loads the I
C controller shifts the remainder of the first byte of the address and 
C slave sends an Acknowledge by pulling the SDA signal Low during the next
W = 0
2
C Data Register.
2
STOP
C Control Register.
). The least-significant bit must be 0 for the write operation.
A
bit and clearing the
2
Slave Address
C Status Register, sets the
P R E L I M I N A R Y
2nd Byte
TXI
START
2
START
C controller sets the ACK bit in the I
MODE
bit of the I
2
C Shift Register with the contents of the 
bit of the I
field in the I
condition to the I
MODE
TXI
2
A
C Data Register is empty.
2
C Control Register to enable transmit 
bit. The I
field selects the address width for this mode
11110XX
2
STOP
C Control Register.
Data
2
C Mode Register for 
ACKV
condition on the bus, and clears 
2
2
Z8 Encore! XP
C controller flushes the second
. The 2
C Slave.
A
bit, and clears the
2
XX
C bus protocol allows the
Product Specification
Data
I2C Master/Slave Controller
2
C controller sets 
bits are the two most
2
C Status Register.
®
F1680 Series
A/A
ACK
bit in 
F/S
224