Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 129

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 63. Timer 0–2 Status Register (TxSTAT)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Timer 0–2 Status Registers
NEF
R/W
7
0
PWM0UE—PWM0 Update Enable
This bit determines whether writes to the PWM0 High and Low Byte registers are 
buffered when TEN = 1. Writes to these registers are not buffered when TEN = 0 
regardless of the value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 
1 = Writes to the Channel High and Low Byte registers are not buffered 
TPOLHI—Timer Input/Output Polarity High Bit
This bit determines if timer count is triggered and captured on both edges of the input
signal. This applies only to DEMODULATION mode.
0 = Count is captured only on one edge in DEMODULATION mode. In this case, 
1 = Count is triggered on any edge and captured on both rising and falling edges of 
Reserved—Must be 0
TCLKS—Timer Clock Source
0 = System Clock
1 = Peripheral Clock
The Timer 0–2 Status (TxSTAT) indicates PWM capture/compare event occurrence, 
overrun errors, noise event occurrence and reload timeout status.
NEF—Noise Event Flag
This status is applicable only if the Timer Noise Filter is enabled. The NEF bit will be
asserted if digital noise is detected on the Timer input (TxIN) line when the data is 
being sampled (center of bit time). If this bit is set, it does not mean that the timer 
input data is corrupted (though it may be in extreme cases), just that one or more 
Noise Filter data samples near the center of the bit time did not match the average 
data value.
and only take affect on a timer reload to
when TEN = 1.
edge polarity is determined by TPOL bit in TxCTL1 register.
the Timer Input signal in DEMODULATION mode
Reserved PWM1EO PWM0EO
R/W
6
0
R/W
5
0
P R E L I M I N A R Y
F23H, F27H, F2BH
R/W
4
0
RTOEF
0001H
R/W
3
0
.
Reserved PWM1EF PWM0EF
Z8 Encore! XP
R/W
2
0
Product Specification
R/W
1
0
®
F1680 Series
R/W
0
0
Timers
115