Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 256

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 127. I2CSTATE_H
PS025011-1010
State
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
State Name
Idle
Slave Start
Slave Bystander
Slave Wait
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Slave Transmit Data
Slave Receive Data
Slave Receive Addr1
Slave Receive Addr2
Master Transmit Data
Master Receive Data
Master Transmit Addr1
Master Transmit Addr2
State Description
I
I
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a 
Not Acknowledge instruction.
Master completing STOP condition (SCL = 1, SDA = 1).
MASTER mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
Nine substates, one for each data bit and 
one for the Acknowledge.
Nine substates, one for each data bit and 
one for the Acknowledge.
Slave receiving first address byte (7- and 10-bit addressing)
Nine substates, one for each address bit and one for the
Acknowledge.
Slave Receiving second address byte (10-bit addressing) nine
substates, one for each address bit and one for the
Acknowledge.
Nine substates, one for each data bit and one for the
Acknowledge.
Nine substates, one for each data bit and one for the
Acknowledge.
Master sending first address byte (7- and 10-bit addressing) 
nine substates, one for each address bit and one for the
Acknowledge.
Master sending second address byte (10-bit addressing) 
nine substates, one for each address bit and one for the
Acknowledge.
2
2
C bus is idle or I
C controller has received a START condition.
P R E L I M I N A R Y
2
C controller is disabled.
Z8 Encore! XP
Product Specification
I2C Master/Slave Controller
®
F1680 Series
242