Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 124

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 59. Timer 0–2 PWM1 Low Byte Register (TxPWM1L)
Table 60. Timer 0–2 Control 0 Register (TxCTL0)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Timer 0–2 Control Registers
TMODE[3]
R/W
R/W
7
0
7
0
PWM1H and PWM1L—Pulse Width Modulator 1 High and Low Bytes
These two bytes, {PWM1H[7:0], PWM1L[7:0]}, store the 16-bit captured timer value for
the DEMODULATION mode.
Time 0–2 Control 0 Register
The Timer 0–2 Control 0 (TxCTL0) register together with TxCTL1 register determines
the timer operating mode. It also includes a programmable PWM deadband delay, two bits
to configure timer interrupt definition and a status bit to identify if the last timer interrupt
is due to an input capture event.
TMODE[3]—Timer Mode High Bit
This bit along with the TMODE[2:0] field in TxCTL1 register determines the operating
mode of the timer. This is the most significant bit of the Timer mode selection value. For
more details, see TxCTL1 register description in
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.
10 = Timer Interrupt only on defined Input Capture/Deassertion Events.
11 = Timer Interrupt only on defined Reload/Compare Events.
R/W
R/W
6
0
6
0
TICONFIG
R/W
R/W
5
0
5
0
P R E L I M I N A R Y
F06H, F0EH, F16H
F21H, F25H, F29H
R/W
CSC
R/W
4
0
4
0
PWM1L
R/W
R/W
3
0
3
0
Table 61
Z8 Encore! XP
PWMD
R/W
R/W
on page 111.
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
®
F1680 Series
INPCAP
R/W
R/W
0
0
0
0
Timers
110