Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 179

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
LIN-UART Control 0 Register
The LIN-UART Control 0 Register
UART’s transmit and receive operations. A more detailed discussion of each bit follows
the table.
Table 89. LIN-UART Control 0 Register (U0CTL0 = F42H)
TEN
0 = Transmitter disabled.
1 = Transmitter enabled.
REN
0 = Receiver disabled.
1 = Receiver enabled.
CTSE
0 = The CTS signal has no effect on the transmitter.
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
PEN
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives 
PSEL
0 = Even parity is sent as an additional parity bit for the transmitter/receiver.
1 = Odd parity is sent as an additional parity bit for the transmitter/receiver.
SBRK
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP
0 = The transmitter sends one STOP bit.
1 = The transmitter sends two STOP bits.
LBEN
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
Transmit Enable (TEN)—This bit enables or disables the transmitter. The enable is also
controlled by the CTS signal and the CTSE bit. If the CTS signal is Low and the CTSE bit
is 1, the transmitter is enabled.
BITS
FIELD
RESET
R/W
ADDR
Note: R/W = Read/Write.
an additional parity bit.
—
—
—
—
—
—
—
—
Parity Enable
Transmit Enable
Receive Enable
Parity Select
Stop Bit Select
Clear To Send Enable
Send Break
Loop Back Enable
TEN
R/W
7
0
REN
R/W
6
0
P R E L I M I N A R Y
CTSE
R/W
5
0
(Table
PEN
R/W
89) configures the basic properties of LIN-
F42H, F4AH
4
0
PSEL
R/W
3
0
Z8 Encore! XP
SBRK
R/W
2
0
Product Specification
STOP
®
R/W
1
0
F1680 Series
LIN-UART
LBEN
R/W
0
0
165