Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 212

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Note:
SCK (SSMD = 00,
ESPI Interrupt
MOSI, MISO
Data Register
Shift Register
CLKPOL = 0,
PHASE = 0,
SSPO = 0)
RDRNE
transmitted, the hardware will automatically deassert the SSV and TEOF bits. The second
method is for software to directly clear the SSV bit after the transaction completes. If
software clears the SSV bit directly it is not necessary for software to also set the TEOF bit
on the last transmit byte. After writing the last transmit byte, the end of the transaction can
be detected by waiting for the last RDRNE interrupt or monitoring the TFST bit in the
ESPI Status register.
The transmit underrun and receive overrun errors will not occur in an SPI mode Master. 
If the RDRNE and TDRE requests have not been serviced before the current byte transfer
completes, SCLK will be paused until the data register is read and written. The transmit
underrun and receive overrun errors will occur in a Slave if the Slave’s software does not
keep up with the Master data rate. In this case the shift register in the Slave will be loaded
with all 1s.
In the SPI mode, the SCK is active only for the data transfer with one SCK period per bit
transferred. If the SPI bus has multiple Slaves, the Slave Select lines to all or all but one of
the Slaves must be controlled independently by software using GPIO pins.
displays multiple character transfer in SPI mode.
When character n is transferred via the shift register, software responds to the receive
request for character n-1 and the transmit request for character n+1.
TDRE
Tx/Rx n-1
Tx n
Bit0
Figure 36. SPI Mode (SSMD = 00)
Rx n-1
Bit7
P R E L I M I N A R Y
Bit6
empty
Tx/Rx n
Tx n+1
Bit1
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Bit0
Product Specification
Rx n
Bit7
Tx/Rx n+1
®
F1680 Series
Figure 36
Bit 6
empty

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