Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 138

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Low-Power Modes
Multi-Channel Timer Applications Examples
PS025011-1010
Capture/Compare Channel Interrupt
Operation in HALT Mode
Operation in STOP Mode
Power Reduction During Operation
PWM Programmable Deadband Generation
Multiple Timer Intervals Generation
A channel interrupt is generated whenever there is a successful Capture/Compare Event
on the Timer Channel and the associated CHIEN bit is set.
When the eZ8 CPU is operating in HALT mode, the Multi-Channel Timer will continue to
operate if enabled. To minimize current in HALT mode, the Multi-Channel Timer must be
disabled by clearing the TEN control bit.
When the eZ8 CPU is operating in STOP mode, the Multi-Channel Timer ceases to
operate as the system clock is stopped. The registers are not reset and operation will
resume once Stop Mode Recovery occurs.
Deassertion of the TEN bit will inhibit clocking of the entire Multi-Channel Timer block.
Deassertion of the CHEN bit of individual channels will inhibit clocking of channel
specific logic to minimize power consumption of unused channels. The CPU can still
read/write registers when the enable bit(s) are deasserted.
The count up/down mode supports motor control applications that require dead time
between output signals.
channels operating in count up/down mode.
Figure 18
timer is in Count Modulo mode with reload =
Continuous Compare operation. After every channel compare interrupt, the channel
Capture/Compare registers are updated in the interrupt service routine by adding a
constant equal to the time interval required. This operation requires that the CHUE bit
(Channel Update Enable) must be set in channels 0 and 1 so that writes to the 
Capture/Compare registers take affect immediately.
on page 125 displays generation of two constant time intervals t0 and t1. The
Figure 17
P R E L I M I N A R Y
on page 125 displays dead time generation between two
FFFFH
. Channels 0 and 1 are set up for
Z8 Encore! XP
Product Specification
Multi-Channel Timer
®
F1680 Series
124