Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 302

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
OCD Data Format
OCD Auto-Baud Detector/Generator
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Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
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The On-Chip Debugger (OCD) interface uses the asynchronous data format defined for
RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first),
and 1 Stop bit (see
To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character 80H. The character 80H contains eight continuous bits Low (one Start bit
plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud
Rate Generator accordingly.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
Match of PC to OCDCNTR register (when enabled).
OCDCNTR register decrements to 0000H (when enabled).
The DBG pin is Low when the device exits Reset.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-on reset.
Voltage Brownout reset.
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low when the device is in STOP mode initiates a System Reset.
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
ST
D0
Figure 59
Figure 59. OCD Data Format
D1
P R E L I M I N A R Y
D2
on page 288).
D3
D4
D5
D6
Z8 Encore! XP
D7
Product Specification
SP
®
On-Chip Debugger
F1680 Series
288