Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 233

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
address. The General Call Address (
recognized if the
RD
transaction. The General Call Address and STARTBYTE address are also distinguished by
the
whether the address match occurred on the unique slave address or the General 
Call/STARTBYTE address. The
is read.
If configured via the
addressing, the most significant 7 bits of the first byte of the transaction are compared
against the
addressing, the first byte of the transaction is compared against {
and the second byte is compared against
Arbitration Lost Interrupts
Arbitration Lost interrupts (
is in MASTER mode and loses arbitration (outputs 1 on SDA and receives 0 on SDA).
The I
automatically when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (
I
indicating the end of the transaction. The
whether the bit is set due to a
a new transaction by the same master is expected to follow. This bit is cleared 
automatically when the I2CISTAT Register is read. The Stop/Restart interrupt 
occurs only on a selected (address match) slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (
Not Acknowledge is received or sent by the I
not set in the I
clears by setting the
the I
the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The
Register.
General Purpose Timer Interrupt from Baud Rate Generator
If the I
BIRQ
2
C controller is in SLAVE mode and a
bit in the I2CISTAT Register to determine if the transaction is a Read or Write
RD
2
2
C controller waits till it is cleared before performing any action. In SLAVE mode,
bit in the I2CCTL Register = 1, an interrupt is generated when the baud rate
C controller switches to SLAVE mode when this instance occurs. This bit clears
2
bit. The General Call Address (
C controller is disabled (
SLA[6:0]
2
NCKI
C Control Register. In MASTER mode, the Not Acknowledge interrupt
GCE
START
bit clears in SLAVE mode when software reads the I2CISTAT
MODE[1:0]
bit = 1 in the I2CMODE Register. The software checks the 
bits of the Slave Address Register. If configured for 10-bit slave
P R E L I M I N A R Y
ARBLST
or
STOP
NCKI
STOP
SPRS
IEN
SAM
field of the I
or
bit = 1 in I2CISTAT) occur in MASTER mode when
0000_0000
bit = 1 in I2CISTAT) occur when the I
bit. When this interrupt occurs in MASTER mode,
bit clears automatically when the I2CISTAT Register
bit in the I2CCTL Register = 0) and the 
bit = 1 in I2CISTAT) occurs when the 
GCA
RESTART
STOP
SLA[7:0]
RSTR
) bit of the I2CISTAT Register indicates
2
or
C controller and the
2
C Mode Register for 7-bit slave
bit in the I2C State Register indicates
) and STARTBYTE (
condition. When a restart occurs, 
RESTART
.
Z8 Encore! XP
condition is received, 
Product Specification
11110
I2C Master/Slave Controller
START
0000_0001
,
SLA[9:8]
®
or
F1680 Series
2
C controller 
STOP
) are
,R/W}
bit is
219