MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet - Page 101

• Manufacturer Part Number: MC9S08QG8CDTE
• Description: IC MCU 8K FLASH 10MHZ 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8CDTE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• Package: 16TSSOP
• Family Name: HCS08
• Maximum Speed: 20 MHz
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
DAA
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
DIV
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Source
Form
Compare Accumulator with Memory
A – M
(CCR Updated But Operands Not Changed)
Complement
(One’s Complement) A ← (A) = $FF – (A)
Compare Index Register (H:X) with Memory
(H:X) – (M:M + $0001)
(CCR Updated But Operands Not Changed)
Compare X (Index Register Low) with
Memory
X – M
(CCR Updated But Operands Not Changed)
Decimal Adjust Accumulator
After ADD or ADC of BCD Values
Decrement A, X, or M and Branch if Not Zero
(if (result) ≠ 0)
DBNZX Affects X Not H
Decrement
A ← (H:A)÷(X); H ← Remainder
Exclusive OR Memory with Accumulator
A ← (A ⊕ M)
Divide
Table 7-2. . Instruction Set Summary (Sheet 4 of 9)
M ← (M) – $01
A ← (A) – $01
X ← (X) – $01
M ← (M) – $01
M ← (M) – $01
M ← (M) – $01
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Operation
M ← (M)= $FF – (M)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
EXT
IMM
DIR
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
Object Code
9E D1
9E E1
9E 63
9E F3
9E D3
9E E3
9E 6B
9E 6A
9E D8
9E E8
A1
B1
C1
D1
E1
F1
33
43
53
63
73
3E
65
75
A3
B3
C3
D3
E3
F3
72
3B
4B
5B
6B
7B
3A
4A
5A
6A
7A
52
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
hh ll
jj kk
dd
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd rr
rr
rr
ff rr
rr
ff rr
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
Chapter 7 Central Processor Unit (S08CPUV2)
2
3
4
4
3
3
5
4
5
1
1
5
4
6
6
3
5
6
2
3
4
4
3
3
5
4
1
7
4
4
7
6
8
5
1
1
5
4
6
6
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
rfwpp
p
p
rfwpp
rfwp
prfwpp
prrfpp
ppp
rrfpp
prrfpp
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
p
rfwpppp
fppp
fppp
rfwpppp
rfwppp
prfwpppp
rfwpp
p
p
rfwpp
rfwp
prfwpp
fffffp
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
Cyc-by-Cyc
Details
VH I N Z C
U – –
0 – –
– – – – – –
– – – –
0 – –
on CCR
– –
– –
– –
– –
Affect
1
–
–
99