MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet - Page 43

• Manufacturer Part Number: MC9S08QG8CDTE
• Description: IC MCU 8K FLASH 10MHZ 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8CDTE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• Package: 16TSSOP
• Family Name: HCS08
• Maximum Speed: 20 MHz
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

0x0000
0x0001
0x0002
0x0003
0x0004–
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
4.3
The registers in the MC9S08QG8/4 are divided into these groups:
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register.
user-accessible direct-page registers and control bits.
The direct page registers in
the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold
text. In
and
the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this
unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could
read as 1s or 0s.
Freescale Semiconductor
Address
•
•
•
Table
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Table 4-3
Direct-page registers are located in the first 96 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
High-page registers are used much less often, so they are located from 0x1800 and above in the
memory map. This leaves more room in the direct page for more frequently used registers and
RAM.
The nonvolatile register area consists of a block of 16 locations in FLASH memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset.
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
PTAD
PTADD
PTBD
PTBDD
Reserved
KBISC
KBIPE
KBIES
IRQSC
ADCSC1
ADCSC2
ADCRH
ADCRL
Register Addresses and Bit Assignments
Register Name
4-4, the register names in column two are shown in bold to set them apart from the bit names to
secure memory.
and
Table
KBEDG7
PTBDD7
KBIPE7
ADACT
PTBD7
COCO
ADR7
Table 4-2
4-4, the whole address in column one is shown in bold. In
Bit 7
—
—
0
0
0
0
0
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Table 4-2. Direct-Page Register Summary
KBEDG6
PTBDD6
IRQPDD
KBIPE6
ADTRG
PTBD6
can use the more efficient direct addressing mode that requires only
ADR6
AIEN
—
—
6
0
0
0
0
KBEDG5
PTADD5
PTBDD5
KBIPE5
PTAD5
PTBD5
ADCO
ACFE
ADR5
—
—
5
0
0
0
PTADD4
KBEDG4
PTBDD4
KBIPE4
ACFGT
PTAD4
PTBD4
IRQPE
ADR4
—
—
4
0
0
KBEDG3
PTADD3
PTBDD3
KBIPE3
PTAD3
PTBD3
ADR3
IRQF
Chapter 4 Memory Map and Register Definition
KBF
Table 4-2
—
—
—
3
0
KBEDG2
PTADD2
PTBDD2
IRQACK
KBIPE2
KBACK
PTAD2
PTBD2
ADCH
ADR2
is a summary of all
—
—
—
2
0
Table
KBEDG1
PTADD1
PTBDD1
KBIPE1
PTAD1
PTBD1
IRQIE
ADR9
ADR1
KBIE
—
—
—
1
4-2,
Table
KBEDG0
IRQMOD
PTADD0
PTBDD0
KBMOD
KBIPE0
PTAD0
PTBD0
ADR8
ADR0
Bit 0
—
—
—
4-3,
41