MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet - Page 86

IC MCU 8K FLASH 10MHZ 16-TSSOP

MC9S08QG8CDTE

Manufacturer Part Number
MC9S08QG8CDTE
Description
IC MCU 8K FLASH 10MHZ 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG8CDTE

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
Package
16TSSOP
Family Name
HCS08
Maximum Speed
20 MHz
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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0
Chapter 6 Parallel Input/Output Control
6.4.4
The pins associated with port B are controlled by the registers in this section. These registers control the
pin pullup, slew rate, and drive strength of the port B pins independent of the parallel I/O register.
6.4.4.1
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTBPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.4.2
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTBSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins which are configured as input.
84
PTBPE[7:0]
PTBSE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTBPE7
PTBSE7
Port B Control Registers
Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
Port B Internal Pullup Enable (PTBPE)
0
Port B Slew Rate Enable (PTBSE)
1
7
7
Figure 6-12. Internal Pullup Enable for Port B Register (PTBPE)
PTBPE6
PTBSE6
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)
0
1
6
6
Table 6-8. PTBPE Register Field Descriptions
Table 6-9. PTBSE Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
PTBPE5
PTBSE5
0
1
5
5
PTBPE4
PTBSE4
0
1
4
4
Description
Description
PTBPE3
PTBSE3
3
0
3
1
PTBPE2
PTBSE2
0
1
2
2
PTBPE1
PTBSE1
Freescale Semiconductor
0
1
1
1
PTBPE0
PTBSE0
0
1
0
0

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