MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet - Page 85

IC MCU 8K FLASH 10MHZ 16-TSSOP

MC9S08QG8CDTE

Manufacturer Part Number
MC9S08QG8CDTE
Description
IC MCU 8K FLASH 10MHZ 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG8CDTE

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
Package
16TSSOP
Family Name
HCS08
Maximum Speed
20 MHz
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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0
6.4.3
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.3.1
6.4.3.2
Freescale Semiconductor
PTBDD[7:0]
PTBD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTBDD7
PTBD7
Port B Registers
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
Port B Data (PTBD)
0
Port B Data Direction (PTBDD)
0
7
7
Chapter 4, “Memory Map and Register
PTBDD6
PTBD6
0
0
6
6
Figure 6-11. Data Direction for Port B (PTBDD)
Table 6-7. PTBDD Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Table 6-6. PTBD Register Field Descriptions
Figure 6-10. Port B Data Register (PTBD)
PTBDD5
PTBD5
0
0
5
5
PTBDD4
PTBD4
0
0
4
4
Description
Description
Definition,” for the absolute address assignments
PTBDD3
PTBD3
3
0
3
0
PTBDD2
PTBD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTBDD1
PTBD1
0
0
1
1
PTBDD0
PTBD0
0
0
0
0
83

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