MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet - Page 37

• Manufacturer Part Number: MC9S08QG8CDTE
• Description: IC MCU 8K FLASH 10MHZ 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8CDTE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• Package: 16TSSOP
• Family Name: HCS08
• Maximum Speed: 20 MHz
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

3.6
One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set.
In any stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the
reference clocks running. See
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
interrupt (RTI), LVD, ADC, IRQ, or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
3.6.1.2
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
Freescale Semiconductor
1
2
STOPE
ENBDM is located in the BDCSCR which is only accessible through BDC commands; see
Status and Control Register
When in Stop3 mode with BDM enabled, the S
0
1
1
1
1
1
Stop Modes
shows all of the control bits that affect stop mode selection and the mode selected under various
Stop3 Mode
LVD Enabled in Stop Mode
Active BDM Enabled in Stop Mode
ENBDM
1
0
0
0
0
x
1
Chapter 17, “Development
Both bits must be 1
LVDE
Either bit a 0
Either bit a 0
Either bit a 0
(BDCSCR)”.
Chapter 10, “Internal Clock Source
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
x
x
LVDSE
Table 3-1. Stop Mode Selection
PDC
x
x
x
0
1
1
IDD
will be near R
PPDC
Support.” If ENBDM is set when the CPU executes a
1
0
x
x
x
x
Stop modes disabled; illegal opcode reset if STOP
instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
Stop1
IDD
levels because internal clocks are enabled.
(S08ICSV1),” for more information.
Stop Mode
2
Section 17.4.1.1, “BDC
Chapter 3 Modes of Operation
Table
3-1. The
35